Many portable electronic devices, such as cameras, cellular telephones, personal digital assistants (PDAs), MP3 players, computers, and other devices include an imaging device for capturing images. One example of an imaging device is a CMOS imaging device. A CMOS imaging device includes a focal plane array of pixels, each one of the pixels including a photosensor, for example, a photogate, photoconductor or a photodiode overlying a substrate for accumulating photo-generated charge in the underlying portion of the substrate. Each pixel has a readout circuit that includes at least an output transistor and a charge storage region connected to the gate of the output transistor. The charge storage region may be constructed as a floating diffusion region. Each pixel may include at least one electronic device such as a transistor for transferring charge from the photosensor to the storage region, one device, also typically a transistor, for resetting the storage region to a predetermined charge level prior to charge transference, and a row select transistor for selectively connecting the pixel to a column line.
In a CMOS imaging device, the active elements of a pixel perform the necessary functions of: (1) photon to charge conversion; (2) accumulation of image charge; (3) resetting the storage region to a known state; (4) transfer of charge to the storage region accompanied by charge amplification; (5) selection of a pixel for readout; and (6) output and amplification of a signal representing a reset level and pixel charge. Photo charge may be amplified when it moves from the initial charge accumulation region to the storage region. The charge at the storage region is typically converted to a pixel output voltage by a source follower output transistor.
In general, CMOS imaging devices require some minimum number of horizontal and vertical lines per pixel for providing control signals, biasing and readout of the pixels. The number of horizontal and vertical lines per pixel running across the pixel array determines the size of the opening over the photosensor and thus, significantly affects fill factor and quantum efficiency.
FIG. 1 shows one column of a typical pixel array 11 as is known in the art. The pixel array 11 contains pixels 50 that are coupled to two vertically routed, conductive/metal lines: column line 45 and array pixel voltage supply line 44. A sample and hold circuit 46 is coupled to the column line 45 for receiving and holding output signals from selected pixels, usually pixel row by pixel row.
FIG. 2 shows the configuration of a typical four transistor pixel 50. The pixel 50 includes a photosensor 52 (e.g., photodiode), transfer transistor 54, and readout circuit 51. The readout circuit 51 includes a storage node configured as a floating diffusion region FD, reset transistor 56, source follower transistor 58 and row select transistor 60. The photosensor 52 is connected to the floating diffusion region FD by the transfer transistor 54 when the transfer transistor 54 is activated when the transfer select line 53 carries a transfer select signal TX. The reset transistor 56 is connected between the floating diffusion region FD and the array pixel voltage supply line 44 supplying the array pixel supply voltage Vaapix. A reset select signal RST supplied over a reset select line 57 is used to activate the reset transistor 56, which resets the floating diffusion region FD to a known state (e.g., Vaapix) as is known in the art.
The source follower transistor 58 has its gate connected to the floating diffusion region FD and is connected between the array pixel voltage supply line 44 and the row select transistor 60. The source follower transistor 58 converts the charge stored at the floating diffusion region FD into an electrical output signal. The row select transistor 60 is controllable by a row select signal ROW, supplied over a row select line 61, for selectively outputting the output signal OUT from the source follower transistor 58 to the sample and hold circuit 46 via the column line 45. For each pixel 50, two output signals are conventionally generated, one being a reset signal Vrst generated after the floating diffusion region FD is reset, the other being an image or photo signal Vsig generated after charges are transferred from the photosensor 52 to the floating diffusion region FD. The reset signal Vrst is selectively stored in the sample and hold circuit 46 when the reset sample and hold select signal SHR is pulsed. The pixel signal Vsig is selectively stored in the sample and hold circuit 46 when the pixel sample and hold select signal SHS is pulsed. Thus, the pixel 50 has two vertical conductive/metal lines that run through each column of the array: array pixel voltage supply line 44 and column line 45, and three horizontal conductive/metal lines that run through each row of the array: transfer select line 53, reset select line 57 and row select line 61.
To increase fill factor, it is often desirable for pixels to share horizontal and/or vertical lines. One known method of sharing vertical lines is for two or more pixels in different columns to share the same column line. Another known method has pixels in adjacent columns sharing the array pixel voltage supply line. Both of these approaches increase fill factor and quantum efficiency compared to the conventional pixel array 11 shown in FIG. 1. As the total pixel area continues to decrease due to desired scaling, however, it becomes increasingly important to create imaging devices with fewer metal lines running through the pixel array area to further increase quantum efficiency and fill factor.